1. Field of the Invention
This invention relates to a graphic processing system which divides graphic data divided in an arbitrary block unit into optimal blocks so that the data quantity becomes a quantity processable by a processing portion, and executes a conversion process on the graphic data (design data) to generate mask production data.
Further, this invention relates to a parallel processing system using a network which executes a conversion process on design data for LSIs, etc, to generate mask production data for exposure by parallel processing by a plurality of processing units connected to a main processing unit by a network.
2. Description of the Related Art
A graphic processing method which converts graphic data for LSI design, for example, to mask production data for plotting (exposure) and plots a circuit design pattern onto a reticle, a mask, a wafer, etc, on the basis of the mask production data, by an electron beam exposure apparatus has been used in the past to produce LSIs. As the scale of the LSIs has become greater (VLSIs, ULSIs) and their density has become higher in recent years, a requirement for a reduction in the processing time required for generating the plotting data (exposure data) for producing the LSIs has become stronger.
Therefore, parallel processing has been carried out by dividing the pattern of an integrated circuit into a large number of data processing object areas and allocating these processing object areas to a plurality of processors (CPUs).
As shown in the flowchart of FIG. 6, for example, the graphic data representing the circuit pattern existing in a chip area is divided into arbitrary units in a layer unit as a whole, a plurality of processors execute the graphic processing in the block unit, and when the data quantity exceeding the memory capacity each processor is allocated and overflow develops, the graphic data inside this block is again divided and the graphic processing is again executed.
Various methods are known for dividing the chip area into the blocks and executing the graphic processing. However, no division reference is set forth, in particular. Therefore, when the overflow occurs during the graphic processing inside the divided block, the processing is terminated as a whole at this point of time, or the block is divided once again at this point so as to execute again the graphic processing from the beginning. For this reason, efficiency of the graphic processing is extremely low. However if all the blocks are divided more finely to match those blocks which might cause on overflow, the data input/output processing requires a longer time and invites a drop in the processing speed.
It is therefore an object of the present invention to provide a graphic processing method which solves the problems of the prior art described above, improves data processing efficiency by effectively utilizing file information of the input graphic data, and also improves the data conversion processing speed by optimizing block division.
A method of producing LSIs which executes a conversion processing of data for LSI design, for example, to mask production data for plotting (exposure) and plots a circuit design pattern to a reticle, a mask, a wafer, etc, by an electron beam exposure apparatus on the basis of this mask production data has been employed in the past. However, the requirement for reducing the processing time for generating the plotting data (exposure data) for producing the LSIs has become higher and higher with a greater scale and a higher density of LSIs (the appearance of VLSIs, ULSIs) in recent years.
Therefore, a technology which divides a data area of a chip for each layer into a large number of data processing object areas, and allocates these processing object areas to a plurality of processors for executing a parallel processing has been proposed in, for example, Japanese Unexamined Patent Publication (Kokai) No. 2-232772. This technology divides the data area of an LSI chip into small areas having substantially the same data quantity, thus makes the loads on the parallel processors uniform and executes the parallel processing.
Nonetheless, the prior art technology described above is not yet free from the following problem.
Namely, the LSI pattern data processor described in Japanese Unexamined Patent Publication (Kokai) No. 2-232772 involves the drawbacks that cut-off of the graphic data occurs when a sizing processing on the graphic data is executed by the parallel processors, and the overlap of the graphic data cannot be confirmed. Further, setting of a boundary line for dividing the pattern data area into small areas having substantially the same data quantity in accordance with layout of the LSI chip is complicated, and the processing efficiency of the parallel processing is not sufficiently high.
Because a plurality of parallel processors having similar performance must be installed for the graphic data processing, the design cost increases.
It is therefore an object of the present invention to provide a parallel processing system using a network which solves the problems of the prior art technologies described above, can improve the conversion processing speed of design data to mask production data, and can reduce the cost by efficiently utilizing an existing system.